The present invention relates to a semiconductor memory device including a dynamic random access memory (DRAM), for example.
Hereinafter, a "low latency DRAM cell" using dual word lines and dual bit lines as disclosed in U.S. Pat. No. 5,856,940 will be described with reference to FIG. 20. Each cell of the low latency DRAM includes two transistors as transfer devices and a single storage capacitor as a charge storage device. And each memory cell is connected to two word lines and two bit lines.
FIG. 20 illustrates a circuit configuration for a low latency DRAM cell 100 in the known semiconductor memory device. AS shown in FIG. 20, the memory cell 100 includes first and second transistors 102 and 103 and a storage capacitor 104. The gate, drain and source of the first transistor 102 are connected to a first word line WLa, a first bit line BLa and a storage node 101, respectively. The gate, drain and source of the second transistor 103 are connected to a second word line WLb, a second bit line BLb and the storage node 101, respectively. One of the two electrodes of the storage capacitor 104 is connected to the storage node 101, while the other electrode thereof serves as a cell plate.
As can be seen, the memory cell 100 includes two independently controllable transistors 102 and 103 for one storage node 101. Accordingly, interleaving is possible between accessing the memory cell 100 using the first word line WLa, first transistor 102 and first bit line BLa and accessing the memory cell 100 using the second word line WLb, second transistor 103 and second bit line BLb. That is to say, while one of the two bit lines is being precharged, the memory cell 100 can be accessed using the other bit line. Thus, reading and writing can be performed at high speeds.
In a memory cell with such a configuration, one of the first and second transistors 102 and 103 should be activated by selecting one of the word lines WLa and WLb to start reading or writing. In selecting the word line, a select signal should be externally input from the outside of the semiconductor memory device or two clock signals should be input externally.
To input the select signal externally, however, a circuit for generating the select signal should be provided outside. Also, if the two clock signals need to be input externally from the outside of the semiconductor memory device, then a circuit for generating these two clock signals must be provided outside. Furthermore, any of these requirements leads to an increase in number of input terminals.